The invention relates to an input buffer with CMOS transistors. The invention more particularly relates to an input buffer for TTL level input signals. The invention relates to a synchronous as well as an asynchronous input buffer.
An input buffer of this kind is known from U.S. Pat. No. 4,380,710, which discloses an asynchronous input buffer which comprises CMOS transistors and which is suitable for TTL level input signals. The input buffer is constructed around an inventer which is connected between two supply voltages at the CMOS level. The output of the inverter is assumed to be capacitively loaded. The N-channel transistor and the P-channel transistor of the inverter form part of a controlled leg of a first current mirror and a second current mirror, respectively. The controlled leg of the first current mirror comprises a current source, which supplies a current which varies as a function of the amplitude of the signal on the inerter input.
The controlled leg of the second current mirror comprises a current sink whose current also varies as a function of the signal on the inverter input. The trip-point of the inverter is determined by a reference voltage applied to the inputs of the current mirrors. Because the input signal never reaches the level of the applied CMOS supply voltages, the N-channel and P-channel transistors are never sufficiently turned off for realizing the complete or fast charging or discharging of the capacitive output load to a CMOS supply voltage level. Therefore, when TTL level input signals are applied, the current source and the current sink must realize fast and substantially complete charging or discharging, respectively, of the capacitive output load in order to obtain a voltage swing on the inverter output covering substantially the entire difference between the applied supply voltages.
Drawbacks of the input biffer disclosed in U.S. Pat. No. 4,380,710 are its high current consumption, its large number of components, the necessity of adding a circuit for supplying the stable reference voltage, and its susceptibility to fluctuations in the supply voltages which are liable to cause incorrect signals on the output of the input buffeer.
SUMMARY OF THE INVENTION
It is an object of the invention to provide an input buffer which is driven by clock signals (in the synchronous case) or not (in the asynchronous case), which comprises CMOS transistors, which is fast (rise time in the order of 5 nsec), which is constructed using a small number of elements, whose trip-point is less susceptible to supply voltage fluctuations, and which does not require an external circuit for supplying a stable reference voltage.
To achieve this, a CMOST input buffer in accordance with the invention is characterized in that it comprises:
a first current source which is connected to a first supply terminal and which comprises a first current output; PA1 a first logic gate which is connected between the first current output and a second supply terminal; and PA1 a first buffer capacitance which is connected between the first current output and the second supply terminal.
A supply voltage which equals the voltage across the first buffer capacitance is present across the first logic gate in the CMOST input buffer in accordance with the invention. A capacitive load to be driven is connected to the output of this gate. If said first current source were absent, then, in the case of variations of the input signals, the gate would continue to transfer charge from the buffer capacitance to the capacitive load and from the capacitive load to the second supply terminal until the supply voltage drops below the limit value where all upper P-channel transistors which are present in the gate and which have a main electrode connected to the buffer capacitance remain turned off, regardless of the amplitude of the signals received on their control electrodes. As from that instant, the capacitive load would no longer receive a charge and, once discharged, it would remain discharged. The loss of charge of the buffer capacitance due to the transfer to the capacitive load, therefore, must be compensated for by current supply to the buffer capacitance. When it is assumed that all upper P-channel transistors receive a high-level voltage V.sub.H on their control electrodes, the current supply will charge the buffer capacitance until the difference between the voltage across the buffer capacitance and the high level V.sub.H exceeds a threshold voltage V.sub.TP of an upper P-channel transistor. At that instant this transistor is turned on. For P-channel transistors connected in series with the latter transistor, a similar consideration holds good when they also receive a high-level voltage V.sub.H on their respective control electrodes. Ultimately, a DC path to the second supply terminal is thus formed and a steady state arises in which the current supply to and the current drain from the buffer capacitance are balanced. The value V.sub.st of this stable voltage in the case of a high input voltage V.sub.H on all upper transistors, therefore, is larger than the sum of V.sub.H and the threshold voltage V.sub.TD.
The capacitive load on the output of the first logic gate is formed by an input of a second logic gate with CMOS transistors. The order of magnitude of this capacitive load is 10.sup.-12 F. A voltage across this capacitive load, which is interpreted by the second gate as being a high CMOS level, should be higher than 2.5 V. This high level arises when the charge present across the first buffer capacitance is distributed between this buffer capacitance and the capacitive load. It is assumed that the initial voltage across the capacitive load equals zero. The redistribution of the charge determines the initial value of the high output voltage of the first gate, while the current source ensures that this output level continues to rise due to the supply of charge to both capacitances. The fact that the stable voltage V.sub.st is larger than (V.sub.H +V.sub.TP) determines the order of magnitude of the buffer capacitance in conjunction with the given order of magnitude of the capacitive load (10.sup.-12 F) and the requirement that the initial value of the high output voltage should be higher than 2.5 V. Utilizing TTL input signals and a threshold voltage of 1 V, this leads to a buffer capacitance of at least from 3 to 5 times that of the capacitive load. For an input signal frequency of 10 MHz, approximately 20 .mu.A is then drained from the buffer capacitance; this charge must be replenished by a current source of approximately 20 .mu.A. It is to be noted that the susceptibility to supply voltage fluctuations of the input buffer in accordance with the invention is low as a result of the smoothing effect of the buffer capacitance.
A preferred embodiment of a CMOST asynchronous input buffer in accordance with the invention is characterized in that a second inverter is connected to a gate output of the first logic gate, which second inverter is arranged between the first and the second supply terminal. The use of this second CMOS inverter as an output stage offers the advantage that its output reaches a high level more quickly than the output of the first gate, because the high level on the latter output increases slowly from a value slightly above 2.5 V when a small current is applied. An additional advantage is that the first logic gate as well as the second CMOS inverter can be proportioned as standard CMOS gates.
In the case of synchronous input buffers for data and clock signals use cannot be made of a separate input buffer for the data and a separate input buffer for the clock signals without introducing additional delays. Because of process tolerances during the manufacture of the individual input buffers and the occurrence of temperature gradients during use, the phase relationship between the data and the clock signals is liable to be disturbed. In order to ensure that the phase relationship is maintained, the synchronous input buffer in accordance with the invention utilizes the structure of a master-slave flipflop.
A preferred embodiment of a CMOST synchronous input buffer in accordance with the invention is characterized in that it includes a first logic gate which comprises a clock signal input and a data input, which first logic gate forms part of a master-slave flipflop comprising a plurality of logic gates, the first and the second supply input of at least the first logic gate being connected to the first current output and the second supply terminal, respectively.